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WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes

来源:Arxiv_logoArxiv
英文摘要

WebRISC-V is a web-based educational tool designed to simulate the pipelined execution of assembly programs according to the RV64IM specifications (64-bit RISC-V processor). The tool allows users to investigate pipeline stalls, understand the internal state of pipeline architectural blocks, and visualize the cycle-by-cycle execution of instructions. WebRISC-V executes directly in a web browser, providing a detailed pipeline execution for RISC-V processors. This paper describes the features of WebRISC-V, compares it with similar tools, and provides an example of its usage in investigating the pipeline.

Roberto Giorgi、Gianfranco Mariotti

计算技术、计算机技术

Roberto Giorgi,Gianfranco Mariotti.WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes[EB/OL].(2025-03-30)[2025-05-01].https://arxiv.org/abs/2504.03722.点此复制

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