互连层空洞对功率芯片粘接可靠性的影响

With the widespread application of large-scale CMOS image sensor chips in consumer electronics, industrial inspection, medical imaging, and aerospace fields, their reliability directly impacts the performance and lifespan of the entire packaging system. However, voids are prone to form in the interconnect layer, posing risks of performance degradation or even failure of the chips. To analyze the impact of voids, this paper focuses on the influence of interconnect layer voids on the reliability of large-scale CMOS image sensor chip packaging. Combining theoretical analysis and simulation methods, the study systematically investigates the mechanisms by which the distribution and size of interconnect layer voids affect packaging reliability. By establishing a thermo-mechanical multi-physics model, the research delves into the influence of key parameters in the interconnect layer on thermal conductivity and stress distribution, providing a theoretical foundation for the packaging design of large-scale CMOS image sensor chips.