Prototype of Front End Electronics based on FPGA-ADC for TOF PET detector applications

raditional digitizers for signal readout of PET detectors are based on commercial analog-to-digital converters (ADC). However, the cost and power consumption of an entire electronic readout system based on digitizers for a PET scanner are high. To address this problem, a soft-core ADC based on a field-programmable gate array (FPGA) was proposed. An FPGA-based ADC (FPGA-ADC) combines low loss and high performance. To achieve good performance, the FPGA-ADC requires three calibrations: time-to-digital converter (TDC) length calibration, TDC alignment calibration, and TDC-to-ADC calibration. A prototype front-end electronics based on FPGA-ADC was built to evaluate the performance of time-of-flight positron emission tomography (TOF PET) detectors. Each PET detector consists of a LYSO crystal single-ended coupled to a silicon photomultiplier (SiPM). The experimental results show that the full-width at half-maximum (FWHM) energy resolution for 511 keV gamma photons after saturation correction of the SiPM was 12.3 %. The FWHM coincidence timing resolution (CTR) of the TOF PET detector with the readout of the front-end electronic prototype is 385.2 ps. FPGA-ADC-based front-end electronics are very promising for multichannel, low-cost, highly integrated, and power-efficient readout electronic systems for radiation detector applications.