面向单片三维集成系统的三层核心单元互联拓扑设计
Interconnect Topology for Three-Tier Core Units in Monolithic 3D Systems
马敬鹏 1韩可1
作者信息
- 1. 北京邮电大学电子工程学院，北京市，100876
- 折叠
摘要
面向单片三维集成计算系统中计算层、末级缓存与内存控制器高度耦合所带来的互联复杂性与通信瓶颈问题，提出了一种三层核心单元的层次化互联拓扑设计。该设计以紧耦合的计算单元-末级缓存-内存控制器为基本构成单元，通过构建簇级局部全连接互联结构，实现核心单元内部的低延迟、高带宽通信；同时引入计算通信与存储访问分离的双路由节点机制，有效降低不同通信域之间的资源竞争。在全局层面，采用以单元簇为节点的二维环面互联网络，在保证可扩展性的同时降低平均通信跳数，并结合垂直互连通道优化跨层数据传输路径。结构分析表明，该互联拓扑在缩短访存路径、提升带宽利用率及增强系统并行通信能力方面具有显著优势，为单片三维集成体系结构中高效计算-存储协同提供了一种可扩展的互联设计方案。
Abstract
To address the interconnect challenges caused by the tight coupling of compute layers, last-level caches, and memory controllers in monolithic 3D integrated systems, a hierarchical interconnect topology for three-tier core units is proposed. The design organizes tightly coupled compute elements, last-level caches, and memory controllers into cluster-based core units with local full-connect interconnects, enabling low-latency and high-bandwidth intra-cluster communication. A dual-router mechanism is further introduced to separate compute and memory traffic, reducing contention between different communication domains. At the global level, clusters are interconnected using a two-dimensional torus network, which lowers average hop count while maintaining scalability, and vertical interconnects are employed to optimize cross-tier data transfer. Analysis shows that the proposed topology shortens memory access paths, improves bandwidth utilization, and enhances parallel communication efficiency in monolithic 3D systems.关键词
计算机系统结构/单片三维集成/片上网络/分层互联拓扑Key words
Computer System Architecture/Monolithic 3D Integration/Network-on-Chip/Hierarchical Interconnect Topology引用本文复制引用
马敬鹏,韩可.面向单片三维集成系统的三层核心单元互联拓扑设计[EB/OL].(2026-03-02)[2026-03-03].http://www.paper.edu.cn/releasepaper/content/202603-23.学科分类
计算技术、计算机技术
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