A time scaling theory for multi-layer electronic systems
A time scaling theory for multi-layer electronic systems
摘要
For six decades, Moore's geometric scaling drove progress in semiconductors. That industry compact no longer holds: returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling. This perspective argues for a successor scaling principle — τ scaling —that adopts time itself, rather than transistor area, as the primary metric of progress, applying a single characteristic time constant τ as the unifying optimization target across twelve orders of magnitude, from a switching transistor to a data-center workload. Two production-scale demonstrations are presented. On a mobile SoC, LogicFolding — a methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers — delivers a 55% step-wise increase in transistor density and a 41% power-efficiency gain at a fixed device node. On AI systems, a co-designed stack comprising the memory-semantic Unified Bus fabric, near-packaged Hi-ONE optical I/O, and edge-to-surface 3D Folding projects more than 100× growth in hardware integration by 2035.The deeper claim is methodological: τ scaling is the first scaling principle since Dennard to establish a shared optimization target across the entire computing stack.
Abstract
For six decades, Moore's geometric scaling drove progress in semiconductors. That industry compact no longer holds: returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling. This perspective argues for a successor scaling principle scaling that adopts time itself, rather than transistor area, as the primary metric of progress, applying asingle characteristic time constant as the unifying optimization target across twelve orders of magnitude, from a switching transistor to a data-center workload. Two production-scale demonstrations are presented. On a mobile SoC, LogicFolding a methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers delivers a 55% step-wise increase in transistor density and a 41% reduction in power consumption at equivalent performance at a fixed device node. On AI systems, a co-designed stack comprising the memory-semantic Unified Bus fabric, near-packaged Hi-ONE optical I/O, and edge-to-surface 3D Folding projects more than 100 growth in hardware integration by 2035.The deeper claim is methodological: scaling is the first scaling principle since Dennard to establish a sharedoptimization target across the entire computing stack.关键词
Time Scaling/τ scaling/LogicFolding/Semiconductor/Electronic systems/New semiconductor pathKey words
τ scaling/ LogicFolding/ gear ratio/ wafer-to-wafer hybrid bonding/ Unified Bus/ Hi-ONE引用本文复制引用
Tingbo He.A time scaling theory for multi-layer electronic systems[EB/OL].(2026-07-03)[2026-07-05].https://chinaxiv.org/abs/202605.00224.学科分类
半导体技术/微电子学、集成电路/电子元件、电子组件
