Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology
Wajid Ali Muhammad Hadir Khan Dalton Gaddy Matthew Guthaus
作者信息
Abstract
Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power delivery creates a new option: it adds thick, low-resistance metal layers on the back of the wafer, and the power grid does not consume all of them. Flip-flops remain on the frontside; a backside mesh therefore cannot drive them directly, and every connection passes through a through-silicon via. We present the first design-space exploration of backside clock meshes, implemented in OpenROAD on GT2N, a 2 nm nanosheet technology. Four benchmarks (1,938 to 15,311 flip-flops) are explored with multi-objective Bayesian optimization, and every design point is verified by transistor-level SPICE simulation, since the cyclic mesh cannot be evaluated by static timing analysis. Across all four designs, the backside mesh consistently outperforms an identical frontside mesh, with on average 45% lower skew, 25% lower sink slew, 4.5% lower power, and 28% less frontside clock wiring, and its skew spread under 10,000-sample Monte Carlo is a third of the frontside mesh's.引用本文复制引用
Wajid Ali,Muhammad Hadir Khan,Dalton Gaddy,Matthew Guthaus.Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology[EB/OL].(2026-10-01)[2026-10-12].https://arxiv.org/abs/2610.02401.学科分类
半导体技术
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