基于SOPC的JPEG编码设计

his article is based on SOPC for hardware and software development platform, in-depth understanding of JPEG compression coding based on the design and realization of the basic model in line with the JPEG standard (Baseline Mode) image compression encoder. JPEG encoder is described by Verilog hardware description language, in accordance with the Top-Down and modular design of the various methods of logic components, integrated software, layout and simulation wiring. Studying at SOPC system, in the Altera SOPC hardware and software development environment to build the support of SOPC system to complete the image sensor, JPEG compression IP core, the control of storage devices, select a suitable Nios soft-core to complete the image acquisition, coding, storage functions.