共时双频数字预失真器DB-DDR的FPGA设计与实现
he design and implementation of DB-DDR concurrent dual-band digital pre-distorter on FPGA
本文对共时双频数字预失真器算法FPGA实现方面的技术进行研究。采用了基于DB-DDR多项式的共时双频功率放大器模型。主要从硬件逻辑设计角度对算法进行实现。此外，考虑到实际FPGA器件的特性，本文还给出了相应的优化解决方案，最后对实现后的共时双频数字预失真器DB-DDR模型进行性能测试。
In this paper, we do the research on the concurrent dual-band digital pre-distorter linearization technology based on FPGA. And we used dual-band dynamic deviation reduction memory polynomial as the concurrent dual-band power amplifier's model. Hardware logic are used to achieve it. In addition, we give a optimized solution which is based on the characteristics of FPGA. At the end of this paper, the test results of the concurrent dual-band digital pre-distorter of DB-DDR model are showed
黎淑兰、于翠屏、曾光
微电子学、集成电路电子电路通信
共时双频功率放大器数字预失真B-DDRFPGA
concurrent dual-bandpower amplifierdigital pre-distortionDB-DDRFPGA
黎淑兰,于翠屏,曾光.共时双频数字预失真器DB-DDR的FPGA设计与实现[EB/OL].(2015-12-17)[2025-08-02].http://www.paper.edu.cn/releasepaper/content/201512-928.点此复制
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