基于CMOS 65nm工艺的k-band低噪声放大器设计
3.4dB NF k-band LNA in 65nm CNOS Technology
本论文提出了一种可以实现最低噪声系数的k波段（18-26.5 GHz）LNA 的设计方法。然后根据这种设计方法，在65nm CMOS 混合信号工艺下设计了一个k 波段低噪声放大器。该LNA工作在22.45 GHz时可以20.46 dB的增益，3dB带宽可以达到3.8 GHz。在整个工作带宽内，S11小于-10 dB,S22小于-14 dB。测试出的最低噪声系数（NF）为3.4 dB。整个芯片工作在1.1 V电源电压下，消耗电流11 mA。芯片的面积为710μm×540μm。
his paper introduces a design method for k-band (18-26.5 GHz) LNA with best noise performance. Then a k-band LNA is designed following the design method in 65-nm CMOS mixed signal process. The LNA has a peak gain of 20.46 dB at 22.45 GHz and a 3 dB bandwidth of 3.8 GHz. The S11 is better than -11 dB and S22 better than -15 dB across the band. The measured smallest noise figure (NF) is 3.4 dB. The whole chip consumes 11mA current under 1.1V supply voltage and occupies an area of 710 μm × 540 μm.
许建飞、闫娜
微电子学、集成电路电子电路无线通信
集成电路设计低噪声放大器k波段MOS 工艺
IC DesignLNAk-bandCMOS technology
许建飞,闫娜.基于CMOS 65nm工艺的k-band低噪声放大器设计[EB/OL].(2012-10-10)[2025-08-02].http://www.paper.edu.cn/releasepaper/content/201210-70.点此复制
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