基于FPGA的多码率LDPC码译码器设计与实现

With the capacity-approaching error performance and parallel decoding structure, Low-density parity-check (LDPC) codes have become a preferable channel coding schemes in modern communication systems. In this paper, we propose a semi-parallel decoder architecture for extended irregular repeat accumulate codes based on the offset minimum sum algorithm and shared structure for edge information storage. This structure can not only reduce the computational complexity and resources consumption significantly, but also be extended to decode LDPC codes with different code rates by simply changing parameters. Finally, we have implemented a multi-rate decoder on a Xilinx FPGA V5LX110 and it can work for code length 8064 bits at rate 1/2, 3/4, 7/8. Test results show that the maximum clock frequency of the decoder is 155 MHz and it can achieve superior performance with 15 iterations.