用于粒子物理实验数据传输系统中的高速电荷泵锁相环设计

Based on a UMC 55 nm CMOS process, this paper implements a 10 GHz high-performance charge pump phase-locked loop with high-speed output and low power consumption, which can provide a?high-frequency differential clock for the data transmission system in particle physics experiments. A dual-branch charge pump with an operational amplifier and dummy MOSFETs is designed to reduce the influence of non-ideal factors on the circuit. A high-speed, low-power 64-divider circuit is designed to convert the 10 GHz differential clock output by the phase-locked loop into a 156.25MHz single-ended clock. An?LC voltage-controlled oscillator is designed with a complementary cross-coupled structure, which enables fast start-up with low phase noise. The simulation results show that under the typical process corner, the phase noise of the VCO at 1 MHz frequency offset is -104.14?dBc/Hz. The PLL lock time is about 500ns, the power consumption is 22.34mW, and the peak-to-peak jitter is 6.59ps.