一种消除反馈延迟的全数字锁相环

In order to compensate the feedback unit delay in conventional digital PLL which brings adverse effect to system steady-state and dynamic performance, an improved digital PLL was proposed which refers to ideal digital PLL with no feedback delay and utilizes the present and previous output of PLL to calculate the ideal output. The proposed novel PLL improves the system stability dramatically, makes performance indexes designed in s domain realized closely in z domain and conquers the performance degeneration in conventional PLL with merely two additional multipliers. Simulation and experiment results show that both step response and frequency response of the novel digital PLL accord with that of the ideal digital PLL, and the novel digital PLL improves the performance significantly with low computational burden, which implies its considerable practical value.