Programmable Video Processor with Fast Interrupt Response for MPEG Decoder
Programmable Video Processor with Fast Interrupt Response for MPEG Decoder
n efficient programmable video processor based on the minimips together with fast interrupt response scheme designed to be used for the MPEG decoder is presented in this paper. The overall architecture, as well as the design for the fast interrupt response and exception handling, is discussed. A shadow register and hierarchical interrupt scheme approach is used. An external interrupt controller is developed, and the system is simulated.
n efficient programmable video processor based on the minimips together with fast interrupt response scheme designed to be used for the MPEG decoder is presented in this paper. The overall architecture, as well as the design for the fast interrupt response and exception handling, is discussed. A shadow register and hierarchical interrupt scheme approach is used. An external interrupt controller is developed, and the system is simulated.
李一凡、谢林
微电子学、集成电路计算技术、计算机技术
MIPS Processor Interrupt.
MIPS Processor Interrupt.
李一凡,谢林.Programmable Video Processor with Fast Interrupt Response for MPEG Decoder[EB/OL].(2006-11-24)[2025-08-16].http://www.paper.edu.cn/releasepaper/content/200611-679.点此复制
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