用对角线算法检测MLC NAND Flash的干扰故障

With the rapid progress of semiconductor process, especially in the field of memory IC, process node is reduced every year, and the Fault become more complex. With space shrinking of memory cell, the probability of disturbance fault happening is increasing sharply. The root cause of disturbance fault is originated from the defects in the insulation layer. Disturbance fault has three phenomenon, which named Gate Stress Program, Gate Stress Erasure and Drain Disturbance. This paper introduces the three fault, and the provides a algorithm, which named diagonal algorithm, to test these fault.