基于硬件加速的数字预失真算法研究及FPGA实现

he implemention of digital predistorter requires lots of matrix operations. Compared with CPU to solve the digital predistortion, FPGA has the advantages such as the higher degree of flexibility, the high concurrency which can greatly improve the caclulation speed and better satisfy the real-time communication system. In this paper, the FPGA implementation of digital pre-distortion system has done the relevant algorithm research and structure design. The system uses memory polynomial model and optimizes the QR algorithm in the least square algorithm, making it more suitable for FPGA hardware implementation. Meanwhile, a fixed-point data format with weights is designed and a high-speed multiplier is designed based on DSP48E1 to satisfy the high clock constraint. The real-time calculation of predistortion complex gain is realized in the loading module. The experimental results show that the computation speed of predistortion on FPGA is 10 times higher than that on CPU.