改进的多元LDPC码编译码器的设计与实现

new scheme for FPGA-based multi-LDPC is proposed to improve the efficiency of multi-LDPC code that used on FPGA and reduce its high occupancy problem. QC-LDPC coding algorithm and Mixed-FFT-BP decoding algorithm are used to reduce the capacity of data storage at the time of encoding, and reduce the use of multipliers in decoding process, so that the logic resource consumption is further reduced. Simulation results show that the Mixed-FFT-BP decoding algorithm in the design can reduce use of the multiplier under the condition of ensuring the accuracy of the data during the operation and reducing the quantization error. And the hardware implementation report indicates that this design can keep the performance of code, at the same time reduce the proportion of FPGA resources effectively. Therefore, this design can provide some reference for the application of LDPC code.