OFDM系统中QC-LDPC码译码器的FPGA实现

Because of the performance of high spectral efficiency and resistance to intersymbol interference and multipath interference, orthogonal frequency division multiplexing (OFDM) has been widely used in the new wireless communication standards. In this thesis, we introduce quasi-cyclic LDPC (QC-LDPC) codes into a FPGA platform of OFDM baseband communications to reduce error rate. Due to the special loop form of QC-LDPC, shift registers are used to reduce the matrix storage as well as simplify the circuit structure. After the analysis of the characteristics of several belief propagation decoding algorithms, Mim-Sum decoding algorithm is selected for implementation of decoder on FPGA. A semi-parallel QC-LDPC decoder circuit structure which is applicable to OFDM baseband communication systems is designed on ISE software. We implement the decoder on XILINX Virtex-5 development board using Verilog HDL. The decoder can dynamic continuously process data block.