基于ADF4360-7低相噪频率合成器的设计
esigning of low phase noise frequency synthesizer based on ADF4360-7
本文对集成VCO锁相环芯片ADF4360-7的进行了介绍，对锁相频率合成器的原理和设计方法进行了论述，讨论了环路的相位噪声、杂散、锁定时间与最佳环路参数的选择问题。最后通过计算机仿真和实验来验证了设计方法的可行性，对于锁相跳频源的设计具有一定的指导意义。本文设计的频率合成器的输出频率范围580MHz—630MHz，相位噪声为-92dBc/Hz@10kHz，杂散优于-73dBc。
In this paper，the ADF4360-7 which is an integrated voltage controlled oscillator(VCO) is introduced, then introduced the basic conception and design method of PLL frequency synthesizer . It also discusses the phase noise ,spurious free dynamic range(SFDR),frequency hopping time and the design of optimum loop parameters. Last, the feasibility of these design methods is vindicated by computer simulation and actual experiment. This has a good instructional meaning to the design of PLL frequency synthesizer. Its specifications show as following: output frequency range 580MHz—630MHz, phase noise -92dBc/Hz@10kHz, SFDR -73dBc.
朱庆福、董利芳
微电子学、集成电路电子电路无线电设备、电信设备
频率合成相位噪声F4360-7
Frequency synthesizerPhase noiseF4360-7
朱庆福,董利芳.基于ADF4360-7低相噪频率合成器的设计[EB/OL].(2008-09-10)[2025-08-02].http://www.paper.edu.cn/releasepaper/content/200809-258.点此复制
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