RC校验芯片设计
he design of CRC checkout chip
本文给出了一种基于Verilog HDL 语言的CRC校验芯片设计的方法，循环冗余校验CRC(Cyclic Redundancy Check) 是由分组线性码的分支而来，其主要应用是二元码组。编码简单且误判率很低，在通信系统中得到了广泛的应用。
In this paper,it gives a method of CRC checkout chip design which is based on Verilog-HDL, the CRC is developed from the branch of the linearity grouping code,the main application is in duality code grouping.the code is simple and miscarriage of justice rate is low,so it use very common in the communication systems.
朱江
微电子学、集成电路通信
RCVerilog HDLQuartusⅡ
RCVerilog HDLQuartusⅡ
朱江.RC校验芯片设计[EB/OL].(2006-02-15)[2025-08-23].http://www.paper.edu.cn/releasepaper/content/200602-94.点此复制
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