Bend-Driven Global Routing for Good Manufacturability

While VLSI feature size continues to shrink in the VDSM regime, minimizing vias in integrated circuits is helpful to improve manufacturing yield, get high circuit performance, and reduce layout area. We try to consider the via minimization problem as early as possible in physical design. We propose a routing method focusing on minimizing vias while considering routability and wire length constraint in this paper. That is, in the global routing phase, we minimize the number of bends, which is closely related to the number of vias. Previous work only dealt with very small nets, but our algorithm is general for the nets with any size. Experimental results show that our algorithm can greatly reduce the count of bends for various sizes of nets while meeting the constraints of congestion and wire length.