集成电路测试向量转换中的时序优化技术

With the rapid development of integrated circuit technology, the scale and complexity of integrated circuit design are also increasing, which makes it increasingly difficult for testers to write test vectors manually. Therefore, the test vectors used in integrated circuit testing are generally automatically generated by EDA tools, but the vectors generated by simulation cannot be recognized by ATE. Therefore, the test vectors need to be converted to obtain the vectors that can be recognized by the ATE. This paper proposes a timing optimization technology based on the periodic conversion from VCD to STIL, which converts the VCD vector generated by simulation into STIL vector, and combines timing optimization technology in the conversion, so that the converted test vector timing can make full use of the jump edge provided by the test machine, thereby reducing the size of the converted test vector and improving the efficiency of testing. Experiments show that this method can improve the success rate of vector conversion and reduce the storage depth required for storing vectors, which has certain reference value for testing vector conversion.