数字集成电路综合及物理设计阶段的时序收敛方案

In this paper,a method to achieve timing closure during synthesis and physical design stage of digita IC is discussed. Timing closure is one of the most important task in digital integrated circuit design. As integrated circuit develops into the deep sub-micron period, the size of chip and the complexity of design has increased significantly. As a consequence of this, it becomes more and more difficult to achieve timing closure. This paper has discussed the method to achieve timing closure in synthesis and physical design based on low-level image processing SoC design. This paper firstly introduces the way that Design Compiler and IC Compiler use to perform timing analysis, followed by a discussion of how to use the tool to set reasonable constraints on the design, and finally introduces the solutions to timing violations in various stages. This SoC has finally got timing closure by using this method..