一种基于FPGA的三相锁相环设计方法
esign Method of Three-Phase Phase-locked Loop Based on FPGA
提出了一种可编程逻辑门阵列(FPGA)实现锁相环的设计方法。介绍了包括鉴相器(PD)、环路滤波器(Loop Filter)和压控振荡器(VCO)等在内的锁相环基本结构和工作原理。利用模块化的设计方法,采用硬件描述语言Verilog HDL实现了包括d,q变换、PI滤波器、VCO等模块的设计。基于FPGA硬件逻辑实现的三相锁相环控制器实验结果表明,系统能在五个周期内,稳定锁定相位信息,稳态误差小,这种控制器能满足多电平交直交变换器装置对电压和相位信息实时性和准确性的要求。
design scheme of three phase phase-locked loop controller based on a field programmable gate arrays (FPGA) is presented. This paper introduces basic architecture and principle of this phase-locked loop including phase discriminator, loop filter and voltage controlled oscillator, etc. This scheme integrated d, q transformation, PI loop filter, VCO module and other test modules which were all written in Verilog HDL. Experimental results verify this controller base on FPGA can provides satisfied dynamic and static, as well as, system can lock the phase information on five cycle. The controller can satisfy the multi-level AC-DC-AC converter equipment with real time and accuracy requirements.
陈杰、汪志勇、舒泽亮
变压器、变流器、电抗器电子电路计算技术、计算机技术
电力电子三相锁相环现场可编程逻辑门阵列变换器控制器
power electronicsthree-phase phase-locked loopFPGAconvertercontroller
陈杰,汪志勇,舒泽亮.一种基于FPGA的三相锁相环设计方法[EB/OL].(2012-03-28)[2025-08-17].http://www.paper.edu.cn/releasepaper/content/201203-763.点此复制
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