带有片上补偿电感的CMOS分布式放大器的设计与分析

With the development of the science and advancement of times, the number of communication data improve with a trend of exponent which demands higher speed and larger bandwidth of wire/wireless communication. The distributed amplifier is designed according to the distributed principle and transmission line theory, and overcomes the adverse the effects of parasitic capacitance to conventional amplifier, it becomes the optimal choice in modern high-speed communication integrated circuit for its extremely wide bandwidth and flat gain. This circuit has been designed under TSMC90nm RF CMOS process, it's a two stage cascaded amplifier, where each stage is composed by four gain cells. This design can achieve 18.0dB±1.0dB flat gain from 260M to 27.3GHz and its unity gain bandwidth is 32.5G, while consuming dc power of 78mW. This article focus on analyzing the optimizing effect of the improved structure on flat gain and bandwidth enlargement.