基于脉动阵列和流水线技术的FIR滤波器的FPGA实现
he FPGA Implementation of High Order FIR Filter Based on Systolic Structure and Pipeline Technology
本文提出一种基于脉动阵列和流水线技术的高阶FIR滤波器的FPGA实现方法。脉动结构有效的解决了数字FIR滤波器实时性的问题，但其占用大量的乘法器和加法器资源。流水线技术可以实现资源的有效复用。脉动结构和流水线技术的合理结合既可有效的实现FIR滤波器实时处理数据的要求，又能有效地减少电路资源消耗。
In this paper, an FPGA implementation method of high order FIR filter based on Systolic Structure and Pipeline Technology is proposed. Design FIR Filter using Systolic Structure can get high speed, but it takes large amount of multipliers and adders. Pipeline technology can save resources. Using the proposed structure can not only reach high speed, but also use less resource.
王世虎、莫亭亭
微电子学、集成电路电子电路
FPGAFIR滤波器脉动阵列流水线
FPGAFIR FilterSystolic Structurepipeline
王世虎,莫亭亭.基于脉动阵列和流水线技术的FIR滤波器的FPGA实现[EB/OL].(2008-10-15)[2025-08-03].http://www.paper.edu.cn/releasepaper/content/200810-292.点此复制
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