有限状态机的VHDL优化设计
VHDL Design Strategy for Finite State Machine
在数字逻辑设计中，会经常遇到设计状态机的问题。本文讨论了设计状态机应注意的事项，比较不同结构方式状态机的优缺点，给出了消除毛刺和优化设计的有效途径。
Problem of designing a finite state machine is often met in the digital logic design. This paper discusses some notes in the process of design and does some compare on state machine with different frames. Then it has given the effective approach to remove the burr and optimize the design.
洪国玺、董辉
微电子学、集成电路电子电路
有限状态机 VHDL 描述方式 毛刺
Finite State Machine VHDL Describing Style Burr
洪国玺,董辉.有限状态机的VHDL优化设计[EB/OL].(2007-10-17)[2025-08-11].http://www.paper.edu.cn/releasepaper/content/200710-258.点此复制
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