基于FPGA/CPLD的多功能数字钟的设计
he Design of Multi-function Digital Clock Based on FPGA/CPLD
本文介绍了利用VHDL硬件描述语言结合FPGA/CPLD芯片设计多功能数字钟，并对整个系统的各个模块设计过程作了具体介绍。在MAX+PLUS II开发软件中编译和仿真，并用Altera公司的EPFl0KTC84-4芯片进行了硬件测试。结果表明该设计方法切实可行，具有很强的可移植性。
his text made detail introduction of multi-function digital clock which was designed by VHDL and the programmable parts of FPGA/CPLD .I compiled and imitated the programs designed in the development environment of MAX+PLUS II and carried on a hardware test by EPFl0 KTC84-4 chips of Altera company. The result of imitation show that the method of the design is practical and has reference for study definitely.
付丽娜
电子技术应用微电子学、集成电路电子电路
FPGA/CPLDVHDLMAX+PLUS II多功能数字钟
FPGA/CPLDMAX + PLUS IIVHDLMulti-function digital clock
付丽娜.基于FPGA/CPLD的多功能数字钟的设计[EB/OL].(2010-07-07)[2025-08-02].http://www.paper.edu.cn/releasepaper/content/201007-152.点此复制
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