FPGA design of a cdma2000 turbo decoder
FPGA design of a cdma2000 turbo decoder
This paper presents the FPGA hardware design of a turbo decoder for the cdma2000 standard. The work includes a study and mathematical analysis of the turbo decoding process, based on the MAX-Log-MAP algorithm. Results of decoding for a packet size of two hundred fifty bits are presented, as well as an analysis of area versus performance, and the key variables for hardware design in turbo decoding.
Maribell Sacanamboy Franco、Fabio G. Guerrero
微电子学、集成电路通信无线通信
Maribell Sacanamboy Franco,Fabio G. Guerrero.FPGA design of a cdma2000 turbo decoder[EB/OL].(2014-04-23)[2025-08-25].https://arxiv.org/abs/1404.5929.点此复制
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