基于Virtex-Ⅱ的时钟数据恢复电路的设计
he Design of CDR Circuit Based on Virtex-Ⅱ
高性能的通信质量要求高稳定性和高精度的时钟，然而在传输过程中不可避免会出现时钟的抖动。这些抖动就给传输带来的偏差，因此，对于时钟的恢复是非常有必要的。基于Virtex系列FPGA，设计了用于时钟数据恢复的模电路，经验证该设计电路能有效的恢复输入的时钟数据信号。
n efficient communication requires high stability and high-precision clock, but the clock jitter is inevitable during the transmission. There will be some deviations because of the jitters, so the recovery of the clock is quite necessary. Based on Virtex serial FPGA of Xilinx Company, we designed a circuit which id used to recovery the input clock and data. And it can recover the clock and data efficient by verification.
刘春茂
微电子学、集成电路电子电路通信
时钟数据恢复数字时钟管理器延迟锁定环亚稳态
R，DCM，DLL，metastability
刘春茂.基于Virtex-Ⅱ的时钟数据恢复电路的设计[EB/OL].(2007-10-10)[2025-08-16].http://www.paper.edu.cn/releasepaper/content/200710-107.点此复制
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