基于延迟链复用的物理不可克隆函数电路设计
esign of Physical Unclonable Functions Circuit Based on Delay Path Dumplis Technology
物理不可克隆函数（Physical Unclonable Functions，PUFs）电路通过提取IC制造过程中的工艺偏差（包括氧化层厚度，W/L和随机离子参杂等因素），实现具有唯一性和不可克隆性的密钥。本文提出一种基于延迟链复用的PUFs电路设计方案，其主要特点是采用数学排列组合的方法，实现判决型PUFs电路延迟链的最大化复用，从而有效提高延迟电路的利用率。然后，在TSMC 65nm工艺下利用全定制方法设计128位延迟链复用PUFs电路，面积为30μm×147μm，并分析PUFs电路的可靠性和安全性。实验结果表明，延迟链复用PUFs电路具有良好的随机性，在128位密钥输出时延迟链电路的利用率提高89.6%。
Physical Unclonable Functions (PUFs) exploit the statistical variation of CMOS circuit during manufacture process to generate unclonable secret data. In the paper, compact C2 n delay-based PUFs (C2 n-PUFs) is designed in TSMC 65nm CMOS technology. After configuring the delay-paths, C2 n-PUFs build different data without circuit replace. C2 n combination method exponential decreases the number of delay path with keeping the output data bits. In custom designed, the area of 128-bit C2 n-PUFs is 30μm× 147μm. Experimental results show that the C2 n-PUFs have reliability and randomness features, and improve information density about 89.6%.
汪鹏君、张跃军、李 刚、李建瑞
微电子学、集成电路
物理不可克隆函数延迟复用工艺偏差电路延迟
PUFs CircuitDelay path multiplexingProcess variationCircuit delay
汪鹏君,张跃军,李 刚,李建瑞.基于延迟链复用的物理不可克隆函数电路设计[EB/OL].(2014-09-30)[2025-08-21].http://www.paper.edu.cn/releasepaper/content/201409-391.点此复制
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