基于GPGPU的LDPC解码访存优化技术研究

s powerful error correcting codes, low-density parity-check (LDPC) codes have been adopted by new emerging standards for digital communication; however, their performance gain is constrained due to their huge computation demand. The GPU-based LDPC decoder is a recent hot research subject for its lower cost and better flexibility. We analyze the parallelism property of SPA (sum product algorithm) and propose an easy way to translate the Tanner graph into an interleaver. From a hardware architecture perspective, we propose an efficient up-to-down multi-stage optimization strategy which releases GPU’s acceleration power to its limit gradually. Experimental results demonstrate that balancing computation and memory access, coalescing global memory accessing and aggressive usage of the on-chip high speed resource (e.g., shared memory and registers) can promote the performance significantly. The proposed decoder can achieve 383x-speedup compared to CPU-based decoder and also outperformances existing GPU-based ones in terms of overall performance.