基于改进常系数乘法器的可配置2D FDCT/IDCT实现

In this paper an implementation of 2D FDCT/IDCT using reconfigurable architecture based on improved fixed-coefficient multiplier is presented, which can implement 2D FDCT or IDCT according to requirement . In order to save adders and registers , the representations of coefficients are transformed and partial products are shared by different multipliers . By transforming the parallel multiplications in W.H.Chen algorithm to serial time-sharing multiplications , 15 multipliers are saved in 1D FDCT and 9 in 1D IDCT . To save the hardware cost furthermore, 1D FDCT and 1D IDCT share fixed-coefficient multipliers , control unit and transposed RAM . The FPGA implementation shows that the clock rate can achieve up to 149.25 MHz , and that our design cuts down 34% of hardware cost compared with implementation of 1D FDCT and 1D IDCT using the same algorithm without improvement.