基于良率最大化的高效SOC测试程序开发
EFFICIENT SOC TEST DEVELOPMENT WITH HIGHEST YIELD
本文将讨论一种针对SOC芯片的低成本测试时间减少解决方案，该方案只是在原有的测试平台（V93K）基础上，改良测试方法和提升测试效率，就可以在保证测试精度和稳定性的前提下实现对芯片要求的所有工程/量产测试需求。其最大的优点是大大降低ATE本身的时间成本，提高的芯片的产出，及时占领市场。
his thesis investigates key points of test time reduction solution, This solution is base on test platform (V93000), improve test approach and elevate test efficiency. On the occasion of guarantee the test yield and keep production stability, chips engineering/mass production requirement can be achieved as more as possible. The biggest advantage is: reduce ATE test time largely, improve chips production output, launch in time.
何晖
微电子学、集成电路电子技术应用
良率SOC测试方法Scan参数测试功能测试频率
YieldSoC Test MethodologyScanParameter TestFunction testFrequency
何晖.基于良率最大化的高效SOC测试程序开发[EB/OL].(2013-03-27)[2025-08-18].http://www.paper.edu.cn/releasepaper/content/201303-902.点此复制
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