应用于GSM的快速锁定全数字锁相环设计

his paper presents a fast settling all-digital phase-locked-loop (ADPLL) for GSM application. The proposed design adopts frequency word presetting and adaptive bandwidth control to accelerate locking of the loop, which achieves a 2us settling time and satisfies GSM requirement. Proposed digital controlled oscillator (DCO) achieves a tuning range of 1.1GHz, which covers GSM frequency range over PVT. The proposed DCO also achieves a frequency resolution of 1.632kHz, which is much smaller than GSM channel bandwidth. ADPLL building blocks including TDC, DPFD, DLF are all redesigned for fast settling application. Simulation results also show that ADPLL provides enough noise suppression at frequencies close to output carrier.