基于System Generator数字下变频实现
he implementation of digital down-conversion
Xilinx公司开发的System Generator for DSP是在Matlab/Simulink环境中进行系统建模的一种DSP开发工具。本文通过System Generator for DSP的数字下变频的建模，来表明DSP设计者不需要掌握VHDL（Veriolog）硬件描述性语言以及开发平台细节的情况下，就可以设计出数字下变频部分。本设计通过该方法加速和简化了FPGA的DSP 系统级硬件设计。具有操作简单、设计灵活、效率高等大多优点。
he System Generator for DSP developed by Xilinx.Inc. is a DSP development tool under the Matlab / Simulink modeling environment. Through the System Generator for DSP, the paper models digital down-conversion to show that DSP designers can design digital down-conversion while they do not need to master VHDL (Veriolog) hardware description language as well as the development platform details. The method accelerates and simplifies the FPGA-DSP system-level hardware design, which holds the predominance of simple operation、flexible design and high efficiency.
吴桂琴、程仙珠、程春霞
电子技术应用微电子学、集成电路计算技术、计算机技术
System GeneratorFPGASimulink数字下变频
System GeneratorFPGASimulinkdigital down-conversion
吴桂琴,程仙珠,程春霞.基于System Generator数字下变频实现[EB/OL].(2009-09-15)[2025-08-04].http://www.paper.edu.cn/releasepaper/content/200909-415.点此复制
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