集成电路准三维电容建库
apacitor Building Database of Quasi Three-Dimensional for Integrated Circuit
在集成电路版图设计和布线阶段，需要通过对电路进行时延分析来对设计结果进行调整指导，这样就需要对这两个阶段的电路进行寄生参数提取。本文对集成电路布线后寄生参数提取中的准三维电容提取进行了研究，采用先进的计算模型和精确的计算方法得到互连线间准确的电容值。
uring the design and layout stage of integrated circuit，delay analysis is often exploited to improve the result.Consequently, the parasitic extraction for two stages of this circuit design is in need. This paper introduces the quasi-three-dimensional capacitance extraction after routing for integrated circuit. Advanced calculation models and accurated calculation methods are used to calculate interconnect capacitance.
刘柳、徐宁
微电子学、集成电路
集成电路寄生参数提取电容提取互连线
Integrated CircuitParasitic Extractionapacitance ExtractionInterconnect
刘柳,徐宁.集成电路准三维电容建库[EB/OL].(2011-03-22)[2025-08-02].http://www.paper.edu.cn/releasepaper/content/201103-890.点此复制
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