基于VHDL语言的数字锁相环的设计与实现

he principle of the Digital Phase Locked Loop has been discussed in order to improve the synchronization of the digital communication system and to make the system stable and reliable. Based on the analysis of the characteristic of the analog phase locked loop, the theory of the digital PLL has been introduced, and the system is designed using VHDL. A kind of DPLL bit synchronization implementation method has been designed , all based on digital circuits. In allusion to the character of signal prone to be interfered, an integral circuit is designed instead of a differential circuit. At the same time an adaptive module joins for the purpose of adjusting the controversy of PLL speed of phase adjustment and the ability of disturbance rejection. With the better ability of disturbance rejection, DPLL can adjust the phase rapidly to achieve the locked state.