首页|Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by
Means of Heuristic Scheduling Algorithm
Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm
Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm
微电子学、集成电路
Wladyslaw Szczesniak.Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm[EB/OL].(2008-01-07)[2025-09-24].https://arxiv.org/abs/0801.1029.点此复制
This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling
algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the
global computational demand and provide balanced power dissipation of
computational units of the designed digital VLSI CMOS system during the task
assignment stage. It results in reduction of the average and peak temperatures
of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced
power dissipation of local computational (processing) units and does not
deteriorate the throughput of the whole VLSI CMOS digital system.
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