多码率LDPC码编译码器的FPGA实现

This paper presents an implementation scheme of multi-rate Low Density Parity Check (LDPC) codes Encoder and Decoder. Architecture of LDPC codes encoder is proposed, and the module of check code calculation and the module of storage are optimized. Structure of LDPC codes decoder is proposed. The structure uses semi-parallel computing mode and early detection technology, and shares the module of storage and the module of iterating calculation. Encoder and decoder are implemented based on FPGA using hardware description language according to the optimized algorithm. Implementation results show that the 1944 code-length encoder can effectively support four code rates with low FPGA hardware resource utilization, and its encoding throughput can be up to 4.3 Gbps; the decoder can effectively support four code rates and achieve a good balance between hardware resource utilization and decoding throughput.