基于Virtex-II Pro系列FPGA的动态部分可重构系统设计与实现
esign and Implementation of Dynamical Partial Reconfigurable System Based on Virtex-II Pro FPGA
Xilinx Virtex-II Pro系列FPGA具有支持局部重构的特点。在XC2VP30平台上利用FPGA局部重构技术实现了动态可重构系统。在平台内嵌的PowerPC处理器控制下，通过内部配置访问通道（ICAP）对OPB总线上的IP模块进行动态重构。采用了slice总线宏实现重构模块与静态模块之间的通讯。系统实现了硬件资源的分时复用，有效的提高系统资源利用率。
Xilinx Virtex-II Pro FPGAs support active partial reconfiguration. A partial reconfiguration system is realized on XC2VP30. PowerPC embedded in the XC2VP30 dynamically reconfigures IP modules which are connected to on-chip peripheral bus (OPB) by internal configuration access port (ICAP). Communications between reconfigurable and static modules are implemented with slice bus macro. By using partial reconfiguration, it allows multiple design modules to time-share physical resources, improving the utility of FPGA hardware resources.
邹祎、赵远宁、吴强
计算技术、计算机技术电子技术应用
Virtex-II Pro动态可重构OPB总线IP模块slice总线宏
Virtex-II ProDynamical Reconfigurationon-chip peripheral busIP moduleslice bus macro
邹祎,赵远宁,吴强.基于Virtex-II Pro系列FPGA的动态部分可重构系统设计与实现[EB/OL].(2008-05-05)[2025-08-02].http://www.paper.edu.cn/releasepaper/content/200805-59.点此复制
评论