一种基于动态阈值NMOS的1.2V CMOS模拟乘法器

Based on the four dynamic threshold voltage NMOS transistor and two active resisitor, a novel 1.2V low power CMOS analog multiplier is prensnted in CSMC 0.6靘 DPDM CMOS process. The number of input transistor has been decreased and the biased transistor and circuits have been saved. When the 5MHz input signal VinA with 1.0V peak-to-peak amplitude and the 100MHz input signal VinB with 0.5V peak-to-peak amplitude, the peak-to-peak amplitude of output signal Vout?is about 350mV. The margin between the first order harmonious wave and the third order harmonious wave of the output wave is about 40dB. The frequency bandwidth of the 1.2V CMOS analog multiplier is 375MHz, and the average power supply current is 30霢. The novel analog multiplier can be applied for the design of low power communication integrated circuits.