一种应用于MB-OFDM UWB系统的维特比译码的FPGA设计与实现
FPGA Implementation of a Viterbi decoder applied on MB-OFDM UWB system
在MB-OFDM UWB（多带正交频分复用超宽带）系统中，为了克服传输信道中的干扰和噪声，保证通信系统传输的可靠性，需要采用合适的差错控制编码。本文按照基于MB-OFDM技术的超宽带ECMA-368/369标准，提出一种在FPGA上实现的应用于MB-OFDM超宽带系统的约束长度为7的多码率（1/3,1/2,5/8,3/4）Viterbi译码实现方案，并在Xilinx XC3S1500芯片上进行实现，最后对资源占用，性能方面进行分析。
In the system of MB-OFDM UWB, in order to overcome the channel noise and interference, we have to use appreciate error control coding to ensure the reliability of the communication system. According to ECMA-368 standard, the paper presents an FPGA way to design a Viterbi Decoder with which mult-rate and the constraint length is 7. Finally implemented it on the Xilinx XC3S1500 chip, and analysis the resource consumption, and performance.
陈君波、胡君萍
无线通信通信微电子学、集成电路
Viterbi译码MB-OFDM UWB差错控制编码FPGA
MB-OFDM UWBViterbi DecoderError Control CodingFPGA
陈君波,胡君萍.一种应用于MB-OFDM UWB系统的维特比译码的FPGA设计与实现[EB/OL].(2011-01-04)[2025-08-04].http://www.paper.edu.cn/releasepaper/content/201101-91.点此复制
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