FPGA上并行实现的AES的时钟毛刺故障注入及差分故障分析

Most attacks assume serial implementation of algorithms, but cryptographic algorithms are often implemented in parallel in hardware. In such cases, the effectiveness of fault attacks also needs to be studied. This article implements a platform for clock glitch injection faults on FPGA. A phase-locked loop is used to multiply the system clock signal to obtain a clock signal of the corresponding frequency. This signal is then divided by different degrees. The clock signal obtained through a quarter-frequency division is used as the normal clock cycle, while the clock signal obtained through a half-frequency division has a shorter cycle compared to the quarter-frequency clock, serving as the glitch clock cycle. Therefore, the position of the glitch can be determined by the position of the half-frequency clock signal. The feasibility of this scheme is verified through functional simulation and the parallel implementation of the AES algorithm on FPGA. Subsequently, the differential fault analysis method is used to attempt to extract the key. After 10,000 fault injections, there are 12 faulty ciphertexts that can be used to recover the key. We select 8 of them for key recovery. Experiments show that this method can effectively recover the key, but the number of injections required is increased compared to serial implementation.