GCM算法的FPGA设计与实现

GCM (The Galois/Counter Mode) is mainly composed of block cipher working on CTR mode and a hash function over Galois fields GF(2^128). This paper presents a FPGA-based low space complexity GCM design and implementation which has low resource consumption and can be used in high-speed networks. An FPGA development platform----FPGAnic is developed. On this platform, high-speed network authenticated encryption applications is achieved based on this low space complexity GCM. Authenticated encryption and decryption can work simultaneously on a single platform, and the performance can achieve the line rate of the high-speed networks. Besides, a frame authenticated encryption method with low overhead is proposed. In the FPGAnic platform, the implementation of GCM is tested in the gigabit network, in the case of no packet loss and error, the results show that the output throughput of the GCM can reach the maximum line rate, and the low-complexity GCM implementation can be applied to high-speed network environment.