基于Hyperlynx的DDR3时序的研究与仿真

For the sake of the stability of the system, it is quite a necessity to proceed some precise timing analysis and control during the design process of PCB, analyzing the timing of the source sync system and deriving the inequality of timing constraints from the results. As for the embedded system, Hyperlynx of Mentor Graphics Co., Ltd. is utilized to do the SI simulation in order to obtain the key parameters in the Timing Inequality. By calculating this timing inequality, the timing constraints of the control system. Ultimately, with the post-route simulation by Hyperlynx, the result is verified. The method elaborated previously is also applicabel to other timing designs of high speed digital systems.