窄带dither在流水线ADC中的校正研究

epending on the features of high speed and high accuracy, pipelined ADCs are widely used in wireless communications field. With the development of process and technology, the requests of SFDR (spurious free dynamic range) for ADC in communications are increasingly demanding. However, the non-ideal factors in circuits limit the dynamic performances of pipelined ADCs greatly. In this paper, a narrow-band dither technique to improve the SFDR of pipelined ADCs is introduced. The theoretical basis and realization method of dither were included. And simulations were finished to verify the improvement of dither based on a 12 bit 100 MS/s pipelined ADC which were fabricated in TSMC 90nm CMOS process. This Pipelined ADC achieves an SFDR of 77.97 dB with a 50MHz, 63.25 mV input signal. And with the dither enabled, the SFDR is 84.79 dB，increasing 6.82 dB .This improves the performance of ADC greatly while the SNR almost keep the same.