快速锁定Bang-Bang数字锁相环设计

his paper introduces the structure of the digital phase-locked loop using the Bang-Bang phase detector and the analysis of the locking transient. On the basis of this theory, the trade-off problem between the phase noise jitter and the locking time is effectively solved, anda fast-locking Fractional-N Bang-Bang Digital PLL is designed. A multi-loop structure with feed-forward branches, a nonlinear Gear-Shift algorithm, and a frequency prediction algorithm are used to achieve fast locking performance of the phase-locked loop. The digital phase-locked loop in this design is implemented in 65nm CMOS technology, and its frequency output range is 5.9-7.9GHz. Simulation results show that under 1.2V power supply, the locking time of the PLL is less than 2μs, the phase noise at 1MHz offset is -126.8dBc/Hz, and the overall power consumption is 12.4mW.