大面积集成电路的后端设计的挑战与方法
he Challenge and Method of The Back-end Deisgn of Integrated Circuit with Large Area
通过一款实现FFT运算的芯片设计为例，来讨论在大面积的集成电路的后端设计中遇到的困难和解决方法。该设计的面积最终达到了9528um x 9528um，在时序、面积与功耗、可制造性设计等方面都遇到了挑战，本文主要从综合、布局布线、时钟树综合、天线效应修正等方面着手，解决了以上三个方面的问题，最终得到一个通过验证可以sign-off的设计。
With a design of a chip which is used for FFT operation , this paper will discuss the challenge and method of the back-end design of integrated circuit with large area . As the area of this design eventually reaches 9528um x 9528um , it has challenges of timing , area , power and antenna , and this paper will solve all the questions above from synthesize , place&route , synthesize of clock-tree and antenna . At last this design has passed the sign-off .
谢马迥、桑红石
微电子学、集成电路
集成电路后端设计物理综合布局布线时钟树综合天线效应
integrated circuitback-endphysical synthesizeplace&routesynthesize of clock-treeantenna
谢马迥,桑红石.大面积集成电路的后端设计的挑战与方法[EB/OL].(2015-05-12)[2025-08-25].http://www.paper.edu.cn/releasepaper/content/201505-117.点此复制
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