基于FPGA的信道误码测试设计
design of the bit error rate testing in communication channel based on FPGA
本文介绍了一种基于FPGA信道误码测试设计方案。该设计方案利用VHDL语言实现多种接口类型、多种传输速率和多种伪随机码码型的选择，并且可以模拟信道功能，实现信道误码和信道延时的手动插入。同时采用触摸屏作为人机接口单元，使该方案具有测试内容丰富、测试结果显示直观等特点。
A design of the bit error rate（BER）testing in communication channel is introduced in this paper, which is based on FPGA. This BER design supports different types of interface and trunk rates, and pseudorandom code based on VHDL language. In addition, by inserting the error bit and delay of manually, the characteristics of communication channel can been simulated. And a touch screen is used as the human-computer interface. The solution of BER testing has the advantages of abundant in test range, simple for use, intuitively show of test result, etc.
方琪、胡绍海
通信无线电、电信测量技术及仪器电子电路
信号处理FPGA误码测试信道误码判别
signal processingFPGAbit error rate testingcommunication channelerror detection
方琪,胡绍海.基于FPGA的信道误码测试设计[EB/OL].(2011-05-16)[2025-08-02].http://www.paper.edu.cn/releasepaper/content/201105-376.点此复制
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