卷积码编译码器的VHDL设计

Based on the principle of convolution code, this paper presents the VHDL design of (2,1,3) convolution encoder and decoder which is designed by tail-biting viterbi decoding method. Some efficient measures is given in the process of representing branch metric, path metric, encoding branch updating and storage, decision and output. By using these measures, the hardware resources consumed are decreased, and the decoding speed is increased. This design is simulated on MaxplusII10.2 and downloaded into the EPF10K30RC240-3 FPGA for demonstration. The results showed the correctness and rationality of the design.